Circuit design, analyses and simulations for CMOS RF circuits.
Support of layout and backend checks.
Chip testing and characterizations.
Minimum Requirements
Five or more years in RF and Analog design for CMOS or BiCMOS analog and mixed-signal circuits.
Experience with RF circuits such as LNA, VCO, Mixers, and Transmitters.
Research or work experience designing analog and mixed-signal circuits, such as continuous-time filters (gm-C or active-RC), DC offset cancellation circuits, frequency-tuning circuits, ADCs, DACs, synthesizers and mixers.
Strong background in electromagnetics theory.
Experience with Cadence EDA design and layout tools.
Experience in lab debugging and chip characterization.
MSEE required. Ph.D EE preferred.
Senior Analog Design Engineer (Ref #0202)
Job Description
Circuit design, analyses and simulations for CMOS analog circuits.
Support of layout and backend checks.
Chip testing and characterizations.
Minimum Requirements
Five or more years in RFIC design for CMOS or BiCMOS analog and mixed-signal circuits.
Experiences with RF circuits such as LNA, VCO, mixers, and transmitters.
Research or work experience designing analog and mixed-signal circuits such as continuous-time filter (gm-C or active-RC), DC offset cancellation circuits, frequency-tuning circuit, ADCs, DACs, synthesizers and mixers.
Strong background in electromagnetic theory.
Strong background in transistor noise and matching.
Experience with Cadence EDA design and layout tools required.
Experience in lab debugging and chip characterization.
BSEE required. MSEE or Ph.D. EE preferred.
RFIC Design Engineer (Ref #0203)
Job Description
Circuit design, analyses and simulations for CMOS RF circuits.
Support of layout and backend checks.
Chip testing and characterizations.
Minimum Requirements
Two or more years in RFIC design for CMOS or BiCMOS analog and mixed-signal circuits.
Experiences with RF circuits such as LNA, VCO, mixers, and transmitters.
Strong background in electromagnetic theory.
Experience with Cadence EDA design and layout tools.
Experience in lab debugging and chip characterization.
BSEE required. MSEE or Ph.D. EE preferred.
Analog Design Engineer (Ref #0204)
Job Description
Circuit design, analyses and simulations for CMOS analog circuits.
Support of layout and backend checks.
Chip testing and characterizations.
Minimum Requirements
Two or more years in RFIC design for CMOS or BiCMOS analog and mixed-signal circuits.
Experiences with RF circuits such as LNA, VCO, mixers, and transmitters.
Research or work experience designing analog and mixed-signal circuits such as continuous-time filter (gm-C or active-RC), DC offset cancellation circuits, frequency-tuning circuits, ADCs, DACs, synthesizers and mixers.
Strong background in electromagnetic theory.
Strong background in transistor noise and matching.
Experience with Cadence EDA design and layout tools.
Experience in lab debugging and chip characterization.
BSEE required. MSEE or Ph.D. EE preferred.
RF Applications Engineer (Ref #0205)
Job Description
RF testing and debugging.
Customer support.
Chip testing and characterizations.
Minimum Requirements
Two or more years of experienced in RF systems testing, board design, and customer support.
Strong background in electromagnetic theory, transmission line theory, Smith Charts, and RF test equipments.
Good communications skills.
Experience with cellular phone reference designs desirable.
BSEE required. MSEE or Ph.D. preferred.
RF and Analog Layout/Mask Designer (Ref #0206)
Job Description
Support RF and Analog IC layout in Cadence Virtuoso environment.
Minimum Requirements
Five or more years of experience in analog and RF layout/mask design.
Must be fluent with Cadence Virtuoso and LVS/DRC.
RF ATE Test Engineer (Ref #0207)
Job Description
ATE Test Program Development for RFIC production testing for cellular phones
Minimum Requirements
Five or more years of experience in ATE test program development for analog and RF integrated circuits.
Candidate should be familiar with RF testing concepts such as phase error, EVM, spectral mask measurements, etc.
Experience in cellular phone RFIC testing a plus.
Senior ASIC Design Engineer (Ref #0208)
Job Description
RTL and digital circuit design, analyses, simulations and verification for deep sub-micron mixed-signal CMOS designs.
Responsible for synthesis, timing analysis, power analysis, and post-layout simulation and verification.
Evaluate designs trade-off and comparison analysis in all design aspects.
Perform DFT and generate test vectors.
Minimum Requirements
Five or more years in ASIC and digital design.
Experiences with mixed-signal circuits designs.
Familiar with Verilog and/or VHDL.
Strong background in DSP, mathematical and electromagnetic theories.
Solid understanding of ASIC design methodology from front-end to back-end.
Experience with various EDA design, verification, and layout tools.
Track record of quality designs with multiple complete design cycles.
BSEE required. MSEE or Ph.D. EE preferred.
ASIC Design Engineer ( Ref #0209 )
Job Description
Implement digital communication algorithm in logic.
Utilize Matlab models to develop and design hardware solutions.
RTL design, analysis, and verification of wireless ASIC.
Validate between Matlab models and ASIC design.
Synthesis and timing analysis of both pre and post layout design.
Area and power optimization.
Perform DFT and scan chain insertion and analysis.
Minimum Requirements
BSEE required, MSEE or Ph.D. in Electronics and Communication field preferred.
5+ years experience in ASIC design.
Strong verilog RTL coding skills, synthesis and verification experience.
Thorough understanding of synthesis methodology, timing analysis and closure.
Worked with various EDA tools from Synopsys, Cadence, or other vendors.
Familiar with design for digital communication circuits preferred.
Experienced with design for test techniques and implementation.
Knowledge in wireless communication and experience in embedded microprocessor a plus.
Self starter able to work with both a highly motivated team and independently.
Strong oral and written communication
RF and Systems Applications Manager (Ref #0210)
Job Description
Manager/Lead engineering team to design cellular phone reference designs for GSM/GPRS/EDGE and WCDMA/EDGE
Responsible for full characterization and FTA of cellular phone module
Responsible for RF performance tuning and debugging
Responsible for customer support
Responsible for management of vendors
Minimum Requirements
Five or more years experience in design cellular phone reference designs for GSM/GPRS/EDGE
Expertise and understanding of system including RF and BB
Experience in firmware development and bring-up of cellular phone modules
Experience in bringing GSM/GPRS/EDGE cellular phone designs to production
Experience in FTA testing environment
Experience in DigRF requirements of cellular phones
Detailed knowledge of 3GPP GSM/GPRS/EDGE specifications
Knowledge of 3GPP WCDMA requirements and module design
